Skip to main content
English
中文
Log In
Log in
Log in with ORCID
NTU Single Sign On
Have you forgotten your password?
Home
College of Electrical Engineering and Computer Science / 電機資訊學院
Computer Science and Information Engineering / 資訊工程學系
Cache-aware task scheduling on multi-core architecture
Details
Cache-aware task scheduling on multi-core architecture
Journal
2010 International Symposium on VLSI Design, Automation and Test
Pages
139-142
Date Issued
2010
Author(s)
CHIA-LIN YANG
Yang, T.-F.
Lin, C.-H.
Yang, C.-L.
CHIA-LIN YANG
DOI
10.1109/VDAT.2010.5496710
URI
http://www.scopus.com/inward/record.url?eid=2-s2.0-78049385939&partnerID=MN8TOARS
http://scholars.lib.ntu.edu.tw/handle/123456789/357315
SDGs
[SDGs]SDG9
Type
conference paper
