The Design of A High Gain Amplifier with Negative Resistance in CMOS 0.13-μm and Yield Analysis
Date Issued
2007
Date
2007
Author(s)
Cheng, Fu-Hung
DOI
zh-TW
Abstract
With the growing technique, wireless communication is more and more popular, and the desire of bandwidth is larger and larger. Therefore, the communication in MMW is approached. By the way, owing to the integration of chip, even if the performance of CMOS in MMW is worse than GaAs, we still try to use CMOS to design MMW front-end circuits.
The first part of this thesis is using 0.13-um CMOS process to design a V-band broadband amplifier. Then we using this amplifier to be the core, and apply the negative resistance in to the circuit to make it have the gain-boosting effect. After measurement, we can verify this topology do works. Finally, we try to find out the reason of low frequency oscillation of a CMSDA ( Cascode Multi-Stage Distributed Amplifier ) and the way to solve this problem.
The second part of this thesis, we try to verify the relationship between yield, matching topology, and matching point, and discuss the parameters which may effect the yield in chip.
Subjects
negative resistance, high gain, amplifier, yield
Type
thesis
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