V-band Subharmonic IQ Mixer Using Transformer Coupling and Buffer Amplifier

In this thesis, a buffer amplifier and two subharmonic down-conversion mixers for V-band communication receiver system are designed and fabricated. This thesis starts from introducing buffer amplifier design principles. Then, this thesis introduces different mixer topologies and features, including active, passive, single balanced and double balanced mixers. Finally, this thesis introduces different sub-harmonic mixer topologies and features. Among all the sub-harmonic mixer topology, the sub-harmonic Gilbert cell mixer is the most widely used. This thesis proposes a two stage cascade amplifier using cascode amplifier with common-source amplifier, and successfully implement a low-power, high linearity and low noise buffer amplifier. Then, we propose an improved single balanced harmonic mixer. This mixer uses frequency multiplier to double local oscillation frequency, active load of cross-coupled to enhance conversion gain, and transformer to improve linearity. Finally, this thesis proposes an improved sub-harmonic Gilbert cell mixer, also using transformer to improve linearity, and adding transimpedance amplifier at output stage to reduce sensitivity to next stage’s impedance, and avoid circuit oscillation. In this thesis, buffer amplifier is developed in TSMC 40 nm CMOS technology. The measured 2dB bandwidth is 51.9GHz to 52GHz, and small signal gain is 9.9dB. The minimum noise figure is 4.8dB at 59GHz, input P1dB is -13dBm, IIP3 is -0.5 dBm, and DC power consumption is 11.23mW. The measured results comparing with simulated results have some deviation, due to in-accurate transistor model at high frequency. The sub-harmonic IQ mixer is developed in TSMC 90 nm CMOS technology. The measured conversion gain is -20.5dB, the input P1dB is 1dBm, and the DC power consumption is 13.92mW. The measured results comparing with simulated results have some deviation, and the reason is explained in Chapter 6. Finally, the sub-harmonic IQ mixer using transformer is developed in TSMC 40 nm CMOS technology. This chip is still under fabrication. The simulated conversion gain is -13 dB, input P1dB is -13dB, IIP3 is 4dBm, and DC power consumption is 26.62mW.