Low-power clock-deskew buffer for high-speed digital circuits
Journal
IEEE Journal of Solid-State Circuits
Journal Volume
34
Journal Issue
4
Pages
554-558
Date Issued
1999
Author(s)
Abstract
An IC containing four clock deskew buffers using the delay-locked-loop technology has been fabricated in a 0.6-μm single poly double metal CMOS process. The core chip area is 0.9×0.9 mm2. The maximum operating frequency is 80 MHz, and the total power dissipation of the four deskew buffers is 59 mW for a 3-V supply voltage. The maximum clock skew after deskewing is less than 300 ps, and the peak-to-peak clock jitter is less than 170 ps. The deskew range is 0.5-3.8 ns.
SDGs
Type
journal article