MPEG-4 video bitstream structure analysis and its parsing architecture design
Resource
Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on
Journal
Proceedings - IEEE International Symposium on Circuits and Systems
Journal Volume
2
Pages
II-184 - II-187
Date Issued
2000-05
Date
2000-05
Author(s)
DOI
N/A
Abstract
In this paper, the hardware-oriented structure analysis and an efficient and flexible bitstream parser for MPEG-4 video are presented. The analysis of bitstream structure explores processing requirement and design constraint for bitstream-level processing. The proposed architecture is basically RAM-based that can be reconfigured for various applications. For high bitrate as about 40 Mbit/s, it needs only about 19 MIPS to parse the bitstream. The impact of the proposed architecture on MPEG-4 video is to enhance and extend the processing for bit domain translation and related real time applications.
Other Subjects
Computer architecture; Constraint theory; Random access storage; Standards; Bitstream structure analysis; Motion picture experts group (MPEG); Image coding
Type
journal article
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