Low-Voltage Low-Power CMOS RF Front End Designs for Wireless Communication Application(II) Analysis & Design of Frequency Synthesizer
Date Issued
1999-07-31
Date
1999-07-31
Author(s)
汪重光
DOI
882215E002041
Abstract
This project proposes a modified frequency
synthesizer architecture to improve the phase noise
and convergence speed of the traditional PLL-based
one. The whole architecture includes phase detector,
loop filter, VCO, and frequency divider. Besides, there
is a sub-sampling scheme substituting for parts of the
divider to reduce phase noise. The design aims at the
PHS standard whose requirements are
1.655~1.678GHz, 77 channels, and 300kHz channel
spacing. The simulation results show that this new
architecture can achieve 200kHz loop bandwidth, 18us
switching time, 10dB phase noise improvement and
40mW power dissipation. The circuit is implemented
by SPTM 0.6um N-well CMOS technology,
occupying chip area of 1.9 mm2.
Subjects
PLL
frequency synthesizer
phase
detector
detector
loop filter
VCO
divider
sub-sampling
PHS
Publisher
臺北市：國立臺灣大學電機工程學系暨研究所
Type
report
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