Low Density Parity Check Code Decoder Architecture Study and Design
Date Issued
2009
Date
2009
Author(s)
Huang, Yu-Te
Abstract
This Thesis discusses an error correction technology, Low-Density Parity Check (LDPC) code, as well as its code constructions, encoding methods and decoding algorithms.artially parallel decoder design methodology provides appropriate trade-off between hardware complexity and decoding throughput. Partially parallel decoder also combines the advantages from both the LDPC fully parallel decoder and serial decoder. Many Quasi-Cyclic LDPC codes have been studied and developed. These kinds of QC_LDPC codes not only reduce the memory addressing complexity in a decoder design but also the encoding complexity. Other compatible QC_LDPC codes have also been proposed. In this Thesis, we choose a code construction method similar to [27] to implement a partially parallel decoder suitable for the family of (3, 6)-regular LDPC codes. array of circulant sub-matrices can be used to represent the parity check matrix Hqc of a QC_LDPC code. A family of structured QC_LDPC codes can be constructed by shifting the identity sub-matrix into different circulant sub-matrices. These kinds of QC_LDPC codes are suitable for partially parallel decoder. And its construction provides flexibility in hardware design.
Subjects
partially parallel decoder
ldpc
quasi-cyclic
FPGA
Type
thesis
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