覆晶構裝底填料交界面黏著力的模擬與評估(3/3)
Date Issued
2003-07-31
Date
2003-07-31
Author(s)
DOI
912212E002047
Abstract
Electronic packaging is a very important technology in domestic microelectronics
industry. On the requirement of being light, thin, short, small and low cost, flip-chip
packaging is one of most promising techniques.
Underfill is a must in the flip-chip packaging in order to compensate stresses arising
from the mismatch of CTE (coefficient of thermal expansion) between die and substrate.
Consequently, interfacial adhesions, between underfill and substrate as well as between
underfill and die, are crucial factors on reliability issues of packaging.
In this report, theoretical analysis, numerical modeling and experimental
measurement are combined to investigate mechanical properties of underfill and
interfacial adhesions.
Subjects
Flip chip
interface adhesion
coefficient of thermal expansion
underfill
interface crack
energy release rate
Publisher
臺北市：國立臺灣大學應用力學研究所
Type
report
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