Design and Implementation of High-frequency CMOS Phase-locked Loops
Date Issued
2008
Date
2008
Author(s)
Li, Sin-Jhih
Abstract
This thesis illustrates the implementation of the high frequency phase-locked loops (PLLs). In order to reduce the output jitter, several strategies are presented, which are suitable for high speed PLL design. The thesis is organized as six chapters. The first chapter is the introduction. In chapter 2, the background knowledge for the PLL design is overviewed.n chapter 3, a PLL with multi-phase control architecture is proposed. Since the proposed architecture effectively suppresses the ripple of the controlled voltage, the jitter resulted from the reference feedthrough is decreased. The circuit is implemented with 0.18-μm CMOS technologies and the measured resulted is also included in this chapter.n chapter 4, a PLL with a compact loop filter is presented. The presented architecture is well suited for the implementation of fully integrated PLLs since the required capacitance in the loop filter can be substantially reduced. The jitter performance will be improved because of the absence of offchip components. The circuit is also realized with 0.18-μm CMOS process and the measured resulted is also included in this chapter.n chapter 5, a PLL operated at 30-GHz is designed and simulated. The modified Colpitts VCO is adopted for the reduction of the VCO noise. A regenerative frequency divider is also employed to widen the dividable range at such high frequency. The design process and the simulation results will be illustrated in this chapter.
Subjects
Phase-locked loop
PD
FD
multi-phased control
Type
thesis
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