Optimized Two-layer Power-ground Mesh Layout for Power Integrity Improvement on Wafer-level Package

The next generation wafer-level packaging technology suffers from serious signal and power integrity issues due to lower re-distribution layer (RDL). Because of serious parasitic effects caused by the high-density lower RDL traces, the robust power delivery network is hard to design. Moreover, limited by package design, decoupling capacitors cannot be flexibly put on package; only on-chip decoupling capacitors are available. Thus the power integrity becomes more serious. The study is divided into three parts. First, the best two-layer power-ground mesh layout design is proposed, which can reduce parasitic effects and improve power integrity. Second, the idea that reduces normalized resistance for better eye diagram is proposed. The table with the layout cross-sectional area versus the available longest distance is also given. Third, the signal interlacing layouts are suggested. Use two types of basic adjacent signal interlacing layout cells and the ghost leg algorithm to create any signal interlacing layout pattern in minimum distance and minimum level. Using our design suggestions contributes to the next generation wafer-level packaging technology development, gives design guidelines and increases the overall performance of the circuits.