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College of Electrical Engineering and Computer Science / 電機資訊學院
Electronics Engineering / 電子工程學研究所
Method for adjusting clock domain during layout of integrated circuit and associated computer readable medium
Details
Method for adjusting clock domain during layout of integrated circuit and associated computer readable medium
Date Issued
2010-01
Author(s)
CHIEN-MO LI
J. Y. Wen
CHIEN-MO LI
URI
http://scholars.lib.ntu.edu.tw/handle/123456789/359586
Type
patent