Design of Fast-Settling and Low-Noise Phase-Locked Loops
Date Issued
2011
Date
2011
Author(s)
Chiu, Wei-Hao
Abstract
Phase-locked loops (PLL) are the key component in various systems. According to the operated principles, there are two different PLL types, the integer-N PLL and the fractional-N PLL. Both types are employed under different environments, but each type suffers from the different design tradeoffs. For the integer-N PLL, the selectable reference frequency is associated with specific channel spacing. It then suffers from narrow loop bandwidth when demanding narrow channel spacing, degrading the frequency-settling time. Next, for the fractional-N PLL, it is known that the tradeoff between the quantization noise and the loop bandwidth is always a concern. To address this issue, in this dissertation, two techniques are proposed to enhance both the integer-N PLL and fractional-N PLL. First, this dissertation proposes a fast-settling technique, dynamic phase error compensation, to speed up the settling process. In addition, this dissertation also proposes a quantization-noise-shifting architecture for the fractional-N PLL, which separates the modulation path from the original loop. This allows independent parameter design to lower the quantization noise while employing wide loop bandwidth.
Both techniques were fabricated in TSMC 0.18-µm CMOS. Measured results verify the proposed techniques that effectively improve the performance for each PLL type. For the integer-N PLL with 20-kHz and 40-kHz loop bandwidth, the settling time is faster than 10µs. For the fractional-N PLL, via the proposed quantization noise shifting architecture, it effectively reduces the quantization noise and fractional spurs. The measurement demonstrates that more than 30-dB suppression on quantization noise is reached, furthermore, more than 10-dB improvement for fractional spurs is also achieved.
Subjects
Phase-Locked Loops
Fast-Settling
Quantization noise
Type
thesis
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