A spur-reduction technique for a 5-GHz frequency synthesizer
Journal
IEEE Transactions on Circuits and Systems I: Regular Papers
Journal Volume
53
Journal Issue
3
Pages
526-533
Date Issued
2006-03
Author(s)
Abstract
A spur-reduction technique is presented to achieve low reference spurs for a 5-GHz frequency synthesizer. A dual-path control scheme incorporated with a pair of the proposed smoothed varactors reduces the gain of voltage-controlled oscillator to less than 15 MHz/V, attenuates the spurious tones, and shortens the simulated settling time by 56%. In, addition, a digital frequency-calibration circuit is used to enlarge the tuning range to overcome process variations. A 5-GHz frequency synthesizer has been fabricated fo0r verification in a 0.18-μm CMOS process. It exhibits phase noise of -79 and-113 dBc/Hz at 10-kHz and 1-MHz offset, respectively. The reference spur level of -74 dBc is achieved by using a second-order loop filter. The overall tuning range is 16.3% and power consumption is 36 mW from a 1.8-V supply. The total switching time including digital frequency calibration takes no more than 110 μs. © 2006 IEEE.
SDGs
Type
journal article