A novel method of low temperature, pressureless interconnection for wafer level scale 3D packaging

Wafer level packaging, possessing higher I/O, lower cost, better integration, improved electrical and thermal properties, is the future trend in industries. A novel bonding method using electroless Cu plating in microfluidic system was implemented for wafer level scale packaging and 3D integration. This process featured low temperature, pressureless bonding condition. Via a continuous oscillated flow under low flow rate, highly uniform Cu pillar interconnections in 2inch wafer scale was achieved and the joints morphology showed great consistency among dies. The similar plating rate also revealed uniform mass transportation under current flow parameters. The mechanisms behind the result were also discussed into three serial processes, followed by mass transportation, chemical reaction, and deposition. Aside from planar wafer scale packaging, synchronous multi-chips interconnections in 3D integration was also approved for high competence. So far, dual-layer stacked chips could be bonded simultaneously within one hour using this method. The bonded pillars showed high uniformity without extraneous deposition between each layer. Deposition rates were in resemblance between chips, revealing that plating solution was distributed uniformly in stacked chips. To summarize, a low temperature, pressureless interconnection method showed great potential in wafer level scale packaging and 3D integration for industries in the promising future.