A Spread Spectrum Clock Generator Based on a Fractional-N Frequency Synthesizer
Date Issued
2007
Date
2007
Author(s)
Shen, Ding-Shiuan
DOI
en-US
Abstract
As portable devices are widely used, high-speed serial links connecting hosts and external devices are becoming popular. Reduction of unnecessary radiation like EMI is a very important issue. Dominant noise sources in portable devices are high speed interfaces between signal processing units and the other peripheral storages, e.g., CD/DVD and HDD. Serial AT Attachment (SATA) is one of the most promising technologies providing large bandwidth up to 3Gbps with possible extension to 6Gbps in the near future. In SATA, a spread-spectrum clocking (SSC) technique is specified to reduce the peak EMI emission by spreading the carrier frequency.
Besides EMI peak reduction amount in frequency-domain, it is more important to consider the time-domain impact of SSC since the major concern in serial data transmission is signal integrity in time domain. To achieve this goal, a low jitter 1.5 GHz spread spectrum clock generator (SSCG) is proposed which incorporates an 8-phase VCO and a fractional dual-modulus prescaler (FDMP). This FDMP utilizes a fractional division ratio to obtain a factor of 3/8 for phase step improvement compared with the conventional dual-modulus prescaler. This is implemented in a 0.18um CMOS process. The achieved EMI reduction amount is 14.77dB and the rms jitter is 5.55ps when SSC turned on. A further extension of this architecture is used to implement a 6GHz SSCG in a 90nm CMOS process. An open-loop multiply-by-2 circuit is incorporated into the architecture to ease timing and speed limitations in closed-loop operation. The simulated EMI reduction is 25dB.
Another work, a high speed 40GHz fractional-N frequency synthesizer, is also presented which incorporates a proposed programmable multi-modulus divider (MMD). The MMD is capable of providing a minimum divider step half of that in conventional MMD. Therefore, a reasonable frequency resolution and better system performance can be obtained. This is implemented in a 0.13um CMOS process and the resulted fractional spur is below -50dB.
Subjects
展頻時脈產生器
低抖動
預除器
spread spectrum clock generator
low jitter
prescaler
Type
thesis