A 7GHz, 90ps Domino Logic Adder with an Efficient Testing Circuit
Date Issued
2009
Date
2009
Author(s)
Hsieh, Min-Han
Abstract
With the growth of demand for high-speed and low power processors, it is essential to improve the performance of adders as it is one of the most critical parts of the processors. Some adder architectures are proposed to enhance the speed and power consumption, such as sparse tree of Intel. Intel also sped up the 32-bit adder to 6.4GHz in 65nm technology. In this thesis, we propose a 32bit modified prefix tree adder which consumes only four complex domino logic stages. It is applied to the characteristic of the Domino logic and deep submicron meter CMOS technology, decreasing gate loading but increasing wire loading. In addition, a well arranged and balanced interconnect route is implemented to reduce 70% cross-coupled capacitances. A test chip was fabricated in UMC 90-nm 1.2-V CMOS technology in March 2009, which is operated at 7GHz and with 90ps latency. The total chip area is 430um ? 110um. And by substrate bias, we save power consumption up to 36.5% that caused by leakage current. In this thesis, we also propose a new efficient and precise circuit for testing, including a Phase-Lock-Loop (PLL) and a Delay-Lock-Loop (DLL). PLL is locked at 7GHz as the system clock. There are ten phases in one cycle of the DLL, which is operated at 7GHz. Because DLL is used between inputs and outputs of adder, we can measure the latency precisely by sampling the outputs with different phases.
Subjects
adders
prefix tree
domino logics
high-speed integrated circuits
low power
design for test
Type
thesis
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