A Divider-Less Sub-Harmonically Injection-Locked All-Digital PLL with Self-Adjusted Injection Timing
Date Issued
2014
Date
2014
Author(s)
Tseng, Kai-Hui
Abstract
This thesis consists of two parts. A Divider-Less Sub-Harmonically Injection-Locked All-Digital PLL with Self-Adjusted Injection Timing is proposed in the first part. The sub-harmonically injection-locked technique is adopted to suppress ADPLL phase noise. This ADPLL works with BBPD instead of power-consuming time to digital converter. To lower the power, the dividers and the DSM of this ADPLL are automatically turned off. A self-adjust injection timing technique is proposed in this work to achieve good phase noise and analysis the sub-harmonically injection-locked phase noise model and compares with measurement. This ADPLL is fabricated in a 40nm CMOS technology. Its power consumption is 3.07mW for a supply voltage of 1.1 V. The measured phase noise is equal to –121.94 dBc/Hz at an offset frequency of 1MHz. The integrated rms jitter is 109.4 fs for the offset frequency from 1kHz to 100MHz. The calculated figure-of-merit is equal to –254.35 dB.
A frequency acquisition technique is proposed in the second part. The BBPD samples the output of the ADPLL directly without though any divider loop. This ADPLL uses only a simple bang-bang phase detector without time-to-digital converter when both frequency and phase locking. In addition, the self-adjust injection timing technique is utilized. The ADPLL keeps good phase noise against PVT variation. This ADPLL is fabricated in a 40nm CMOS technology. Its power consumption is 3.04mW for a supply voltage of 1.1 V. The measured phase noise is equal to –121.4 dBc/Hz at an offset frequency of 1MHz. The integrated rms jitter is 109.6 fs for the offset frequency from 1kHz to 100MHz. The calculated figure-of-merit is equal to –254.39 dB.
Subjects
無除頻器
全數位鎖相迴路
Type
thesis
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