Design of a Bi-directional NoC Architecture with Virtual Channel Sharing Mechanism
Date Issued
2011
Date
2011
Author(s)
Yeh, Hsin-Hsien
Abstract
Network-on-Chip (NoC) architecture has been viewed as a possible solution to support the growing design complexity of Multi-Processor System-on-Chip (MPSoCs) since the advent of deep sub-micron technology in recent years. In an NoC design, buffer resources dominate the major power consumption and area overhead of the entire router architecture. How to utilize buffer resources efficiently is always a significant study issue. In this Thesis, we propose a power- and area-efficient router architecture using a Virtual-Channel Sharing (VCS) mechanism to improve the network performance in a Bi-directional NoC (BiNoC) architecture especially under the non-uniform traffic environment. The underlying idea is that each input port in our proposed router can share its idled virtual-channels to the neighboring input ports. In other words, an input port can borrow idled virtual-channels from the adjacent input ports to suffer the temporary high traffic load. The improvement of the routing and virtual-channel utilization flexibility by our proposed VCS mechanism can eliminate the head-of-line blocking efficiently under a constrained number of virtual-channels. The experimental results show that a significant performance improvement, in terms of area overhead and power consumption, can be obtained by our proposed VCS mechanism.
Subjects
Network-on-Chip
NoC
Router
Bidirectional Channel
Virtual-Channel
Load-balance
Buffer
Resource Sharing
Type
thesis
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