The Design and Implementation of a Perl Compatible Regular Expression Pattern Matching Engine with Pipeline Architecture using FPGAs
Date Issued
2008
Date
2008
Author(s)
Chang, Ching-Liang
Abstract
A regular expression is powerful to describe signature patterns used in an Intrusion Detection System (IDS). This paper focuses on how to employ a pipeline architecture to NFA-based hardware implementations in order to increase the system performance. We propose a comparator that shares comparison operators including the ASCII decoder, the static pattern matching, and the char classes, and then we partition the comparator into two stages. As a result, we apply a three-stage pipeline to our Perl compatible regular expression pattern matching engine (PCRE engine) including a two-stage pipeline comparator and a one-stage NFA-based pattern recognizer. In addition, we can easily implement Caret meta-character (means the beginning of a string) when using the three-stage pipeline architecture. Finally, experimental results show that the proposed three-stage PCRE engine has a throughput of 2.4 Gbps as compared with the 1.8 Gpbs of the original PCRE engine in an Altera DE2 platform. This means that the proposed approach can have 30% performance increase in the current implementation with respect to the non-pipeline one.
Subjects
FPGA
Perl Compatible Regular Expression
Pattern
Regular Expression
Type
thesis
File(s)![Thumbnail Image]()
Loading...
Name
ntu-97-R95921085-1.pdf
Size
23.32 KB
Format
Adobe PDF
Checksum
(MD5):d405149c2040085081a556b3305d3499