Low-Noise Frequency Synthesizer for 802.11a
Date Issued
2004
Date
2004
Author(s)
Kuo, Chun-Yi
DOI
zh-TW
Abstract
As various wireless standards continue to populate the 80-MHz spectrum in the 2.4-GHz band, the IEEE 802.11a operating in the 5-GHz unlicensed national information infrastructure (UNII) band which allows high-speed data communications become more attractive and fascinates more realization of wireless link and mobile communication, compared to the 2.4-GHz counterpart.
It has been well acknowledged that integration of an RF frequency synthesizer into a transceiver poses great challenge because the large dynamic range of the input signal and wide channel bandwidths have set stringent requirements for the synthesizer phase noise and spurious sideband levels. To implement an integrated RF frequency synthesizer, phase-locked loops are usually utilized to cope with variations in the device parameters with process and temperature resulting in frequency variations of the voltage-controlled oscillator (VCO). Such implemented VCO nevertheless translates to a quite large gain (KVCO) for the coverage of the wide operating range of IEEE 802.11a. While techniques to avoid large KVCO have been developed, the characteristics of wide-range and low-sensitivity still may not be realized concurrently in that high frequency of 5 GHz. In particular, the KVCO is difficult to design as small as around 20 MHz/V to reduce noise sensitivity of the closed-loop, as is in contrast feasible in 1.8-GHz applications.
To achieve both the two goals within a single frequency synthesizer, a topology composed of a dual-analog-control PLL and a digital frequency-calibration circuit is proposed. Compared with traditional frequency synthesizers, this work exhibits a wide operating range and a reasonable settling speed while performing well on in-band phase noise and reference spurs.
Chapter 2 will give basic ideas of phase-locked loops (PLLs) as well as some important characteristics in a frequency synthesizer. A design flow is described along with detailed parameter setting and Architecture simulations together with some examples are demonstrated.
In chapter 3, the design considerations of this thesis will be introduced. Concerns including spectral purity, operating range, and switching time are all crucial. Detailed analysis of the proposed architecture will be presented thereafter.
Chapter 4 contains the design and implementation of the proposed synthesizer in a CMOS 0.18-μm 1P6M mixed-signal technology.
Chapter 5 will give a conclusion to this work, providing a performance summary and comparison with those works in the literature. Key results together with issues that should be noted for future perspectives are reinforced and summarized.
Appendix A presents a related work – a 5.8-/5.2-/2.4-GHz SiGe LC VCO with wide tuning range. Implemented in a 0.35-μm SiGe BiCMOS technology, this VCO utilizes a hybrid frequency-selecting scheme: by inductive band- switching and capacitive frequency-tuning, this VCO achieves both multi-band and wide range characteristics with a control voltage from 0- ~ 3.3-V.
Subjects
鎖相迴路
頻率合成器
無線區域網路
phase-locked loop
PLL
wireless local area network
WLAN
frequency synthesizer
Type
thesis
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