A Test Clock Reduction Method for Scan-Designed Circuits
Resource
International Test Conference, Washington D.C.(1994.10)
Proceedings of International Test Conference, p.331-339
Journal
International Test Conference, Washington D.C.(1994.10)
Pages
-
Date Issued
1994-10
Date
1994-10
Author(s)
Lin, Chen-Shang
Type
conference paper