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College of Electrical Engineering and Computer Science / 電機資訊學院
Electrical Engineering / 電機工程學系
Gate-Level Dual-Threshold Static Power Optimization Methodology (GDSPOM) for Designing High-Speed Low-Power SOC Applications Using 90nm MTCMOS Technology
Details
Gate-Level Dual-Threshold Static Power Optimization Methodology (GDSPOM) for Designing High-Speed Low-Power SOC Applications Using 90nm MTCMOS Technology
Journal
ISCAS
Date Issued
2006-05
Author(s)
B. Chung
J. B. Kuo
JAMES-B KUO
DOI
10.1109/iscas.2006.1693418
URI
http://scholars.lib.ntu.edu.tw/handle/123456789/325385
Type
conference paper
