An All-Digital Frequency Synthesizer with Statistic TDC
Date Issued
2014
Date
2014
Author(s)
Chung, Yun-Rong
Abstract
In this thesis, an all-digital frequency synthesizer by utilizing novel technique of statistic time-to-digital converter (statistic TDC) is proposed. The proposed statistic TDC applies statistic properties of counters and associated toggle logics. Based on derived statistic model and system architecture, ultra high resolution of the converter is achieved. The minimum resolution can be even smaller than the minimum gate delay of inverter chains available in a process technology. Also, due to intrinsic statistical property, the statistic TDC reveals fully insensitive characteristics against device/process variations of fabrication technology. Therefore, design complexity of matching circuits required in analog converter design can be avoided. According to derived mathematical model, the minimum resolution of proposed statistic TDC can achieve almost unlimited order of magnitude, without considering area and power consumption. The all-digital frequency synthesizer consists of a statistic TDC, a dynamic loop filter, and a high speed locking stage controller. The results of locking time simulation shows that settling time of all 14 channels in ISM 2.4 GHz band are all within 8μs and frequency errors of 14 channels under locking condition are all less than 1ppm.
Subjects
Statistic TDC
ADPLL
Dynamic Loop Filter
Fast Locking Technique
Type
thesis