Capacitors and inductors extraction and schematic generation from layout of passive multilayer microwave circuit
Date Issued
2010
Date
2010
Author(s)
Huang, Shao-Hua
Abstract
This thesis presents a method that can generate schematic from layout of passive microwave multi-layer circuit. There are two parts in this thesis. The first part is about dividing the rectilinear polygon into rectangles that may constitute capacitors and inductors. With user-defined design parameters such as maximum line width and minimum line width, we can classify the rectangles that may be part of a capacitor or a inductor. The second part is about extracting component according to the geometric characteristics of the components. Schematic is then generated according to the connectivities of extracted components in the layout. Designers can then compare the schematic corresponding to the layout with the original schematic for debugging. These two parts are the front-end of layout vs. schematic (LVS) checker.
We implement this method and test it in layouts using LTCC and BCB processes. It can indeed generate the correct schematics from layouts.
We implement this method and test it in layouts using LTCC and BCB processes. It can indeed generate the correct schematics from layouts.
Subjects
layout
LVS
rectilinear
computational geometry
Type
thesis
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