Skip to main content
English
中文
Log In
Log in
Log in with ORCID
NTU Single Sign On
Have you forgotten your password?
Home
College of Electrical Engineering and Computer Science / 電機資訊學院
Electronics Engineering / 電子工程學研究所
Design and Implementation of a Low Power Delay Fault Built-in Self Test Technique
Details
Design and Implementation of a Low Power Delay Fault Built-in Self Test Technique
Journal
VLSI/CAD Symposium
Pages
55
Date Issued
2004-01
Author(s)
CHIEN-MO LI
L. W. Ko
CHIEN-MO LI
URI
http://scholars.lib.ntu.edu.tw/handle/123456789/310817
Type
conference paper