Blockage-Avoiding Buffered Clock-Tree Synthesis with Clock Latency-Range Minimization

Date Issued

2009

Date

2009

Author(s)

Cheng, Chung-Chun

URI

Subjects

Physical Design

Clock Tree

Blockage Avoidance

Slew Rate

Variation Tolerance

Buffer Insertion

Type

thesis

File(s)

Name

index.html

Size

23.27 KB

Format

HTML

Checksum

(MD5):c559e41fd19bc7cfdeaf4bef8831b08c