VLSI Timing Visualization Plus ECO
Date Issued
2011
Date
2011
Author(s)
Wong, Tzi-Chaou
Abstract
Circuit optimization is a very important step in high performance and low power IC design. It has a significant impact on its delay, power dissipation and area of the final
circuit.
The goal of our tool is to let VLSI designers easily repair timing violation problems. We can easily view the circuit by combining the RTL code that is after synthesised and the
timing report from Primetime. We can show designer the critical path, to make sure whether it is what the designer expect. If it’s the same, then congratulation, the designer
get a great circuit after synthesised. But if not,then designer can see what happened. The designer can see, which gate makes the critical path differ from he expected. Then the designer can click the toolbar icon to change the type of gate ( because different type of the same gate have different sizes.) After that, we can response the designer a new RTL code with the gate type changed. Use the new RTL code to run Primetime again, and use the tool to open those two new files. If the designer well changed the type of gate, then the designer will see the different critical path to the previous one. After the steps above, the designer can finally get a well timing circuit they expect.
Subjects
VLSI timing debug
cross intersection reduce
ECO
timing visualization
Type
thesis
File(s)![Thumbnail Image]()
Loading...
Name
ntu-100-R97943153-1.pdf
Size
23.32 KB
Format
Adobe PDF
Checksum
(MD5):17c51788d05e24c3d460b4ff58e0b219