Design and Implementation of Delay-Locked Loops with Static Phase Error Calibration
Date Issued
2009
Date
2009
Author(s)
Teng, Kuang-Fu
Abstract
Conventional CMOS charge-pump circuits have some current mismatch problems. The current mismatch induces a phase error which deteriorates the performance of delay-locked loop systems or phase-lock loop systems. In this dissertation, we describes on the design and application of delay-locked loop systems and we use three architectures and circuits to improve the phase error in the synchronization systems, and there is no extra replica charge-pump needed; these architectures and circuits have been fabricated in 0.18µm CMOS to verify the circuits technique and measure the systems calibration result. Hence, using a digital technique with auto-tracking ability to calibrate the current mismatch of the charge-pump in delay-locked loop systems; and one chip is using a time amplifier[9] to amplify two different input phase and in the other chip, we propose a new switched-delay phase-frequency detector is well suited to the delay-locked loop systems to magnify the phase error in the original system, that increase the phase detectable resolution of phase-frequency detector to fine tune charge-pump calibration. Next, we propose a new technique is digital different reset time of phase-frequency detector circuit to separate UP and Down that are outputs of phase-frequency detector that control charge-pump will charge or discharge reset time, that will shift the location of phase error to achieve in-phase. We design three architectures and circuits can cover 10% process variation, and these are all can improve the phase error. The area of these three chips were all 0.85mm * 1.0mm, and reference frequency is 500MHz and voltage on power supply is 1.8V, the power consumes was less than 30mW.
Subjects
Delay-Locked Loop
Charge-Pump calibration
Phase error calibration
Switched-Delay PFD
Time Amplifier
Different Reset Time PFD
Type
thesis
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ntu-98-J95921053-1.pdf
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