Study on a High Performance Module in Baseband Communication Chips
Date Issued
2004
Date
2004
Author(s)
Hsieh, Po-Chun
DOI
zh-TW
Abstract
In this thesis we present a new delay line circuit design. The structure of delay line we adopt in our design is ring counter based delay line, which consists of a ring counter and a latch array. The ring counter works as an address decoder and the latch array is a storage block.
In order to lower the power consumption of delay line, gated-clock structure is used, but the original gated-clock ring counter structure in the reference still consumes more power. We improve the gated-clock ring counter structure with a new “enable” signal generation circuit to save the power, and the gated-clock driver tree architecture is designed to reduce the load of clock signal. On the other hand, the double-edge-triggered flip flop is also adopted to lower the clock frequency. In the latch-array storage block, the concept of gated driver tree is also used to replace the I/O drivers with multiplexers and demultiplexers. The application of multiplexers and demultiplexers also reduce the load of I/O data.
Subjects
延遲線
環狀計數器
delay line
ring counter
Type
thesis
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