Chip-Package Co-Analysis and Design for SI/PI Issues of High-Speed Memory I/O Interfaces
Date Issued
2010
Date
2010
Author(s)
Hsu, Chih-Jung
Abstract
To obtain better performance in signal integrity (SI) and power integrity (PI) of high-speed memory circuits, the co-analysis and design of chip-package structures under stub series terminated logic (SSTL) topology are demonstrated. Based on the characteristic current flow, three package design parameters: Ldiff, LPDN, and Lloop, are proposed to evaluate the PI and SI performance of high-speed memory input/output (I/O) circuits. The chip-package co-simulation and measurement at time-domain have reached a good agreement in both PI part and SI part to verify the ideas. A systematic design flow is constructed for dynamic random access memory (DRAM) designers to obtain better SI and PI performance. Under the design flow, an application study to improve a commercial DDR3 package, which refines from a real package substrate, is presented to have better performance in SI and PI under the condition of identical layout area. The eye-height of output signal and voltage variation of the worst case have been improved 16.1% and 10.1% at data-rate 5 Gb/s, respectively.
Subjects
stub series terminated logic (SSTL)
signal integrity (SI)
power integrity (PI)
input/output (I/O) circuits
dynamic random access memory (DRAM)
Type
thesis
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