Research of Watt-Level Parallel-Parallel Transformer Combined CMOS Power Amplifier with 3-D Architecture
Date Issued
2016
Date
2016
Author(s)
Luo, Shih-Jyun
Abstract
With the development of wireless communication and the evolution of semiconductor process, the radio frequency integrated circuit implemented in CMOS technology become the focal point in the industry with cost advantage. The power amplifier is the most critical component in the transceiver design. Thus the main focus of this thesis is on the design and analysis of power amplifier in CMOS. The chapter 2 describes a 24 GHz three series-connected (stacked) power amplifier implemented in 90 nm CMOS process. Increasing the supply voltage by stacking FETs to increase the power density per area without sacrificing reliability, and choosing the gate capacitance to generate the proper load impedance of each stacked-transistor by actual simulation. Adopting transformer in input and output terminals to achieve impedance matching, power combining and single to differential ended simultaneously in push-pull topology. The chip size is 0.27 mm2 and output power is 21.7 dBm. The chapter 3 describes a 77 GHz transformer combined power amplifier with 3-D architecture implemented in 90 nm CMOS process. The radial power combiner and splitter achieve the 8-ways power combination to increase output power. The radial power combiner with the function of impedance transformation reduces the impedance transformation ratio of output matching networks and alleviates the loss caused by large impedance transformation ratio. Sharing the center area of the chip to form a 3-D structure and thus the area occupied by the power combiner and power splitter can be reduced. The power cell adopts the transformer to realize power combining, impedance matching and single to differential ended simultaneously. The chapter 4 describes a 5 GHz high output power transformer combined power amplifier implemented in LDMOS process. By parallel-parallel combining transformer technique, the multiple transformers realize in the same area to reduce the area of multiple transformers in multi-way power combination. Thus it can maintain the area as 1-way transformer and function of multi-way power combination simultaneously. And using the 3-D radial architecture described in chapter 3 to further reduce the chip area.
Subjects
Power amplifier
Transformer combining
Stacked transistor
High operating voltage
Type
thesis