A Data Communication Interface Design for Bus and Networks-on-Chip Architecture
Date Issued
2008
Date
2008
Author(s)
Tan, Hsiang-Jen
Abstract
In system-on-chip design, each IP uses shared bus to communicate with the others. With the advance of the present time semiconductor technology and the increasing complexity of the system design, there are getting more and more IP cores. Because shared bus are nonscalable, they are limited in developing, and cannot reach the future system requirement in performance; In recent years, there are many papers proposing Networks-on-Chip (NoC) Architecture to overcome future systems design challenges, because of the higher bandwidth, regularity and modular in network. There are two major components: router and network interface in NoC architecture. Under satisfying the prerequisite of better performance than shared bus by using high data rate, including the traffic on network and the overhead of area, power and latency will be very large; it will often have congestion or hotspots in NoC. There are a lot of papers and researchers improving these problems; we address a new architecture: Hybrid Networks-on-Chip. It is based on NoC, and each switch connects a sub-system that is composed by linking many IPs on AMBA (Advanced Micro-controller Bus Architecture) rather than a single processing element. In this thesis, we propose a simple network interface design that not only transforms the AMBA signals and the packet data in network but helps hybrid architecture to achieve low latency and solve the problem of hop counts and hotspots.
Subjects
Networks-on-Chip
System-on-Chip
Network Interface
Bus
low latency
Type
thesis
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