Publication: Fabrication of GeSn Nanowire MOSFETs by Utilizing Highly Selective Etching Techniques
cris.lastimport.scopus | 2025-05-16T22:29:15Z | |
cris.virtual.department | Electrical Engineering | en_US |
cris.virtual.department | Electronics Engineering | en_US |
cris.virtual.orcid | 0000-0003-4905-9954 | en_US |
cris.virtualsource.department | 7629a287-8c7f-41fd-b71e-fb2b5de8b1b6 | |
cris.virtualsource.department | 7629a287-8c7f-41fd-b71e-fb2b5de8b1b6 | |
cris.virtualsource.orcid | 7629a287-8c7f-41fd-b71e-fb2b5de8b1b6 | |
dc.contributor.author | Hong, TC | en_US |
dc.contributor.author | Lu, WH | en_US |
dc.contributor.author | Wang, YH | en_US |
dc.contributor.author | JIUN-YUN LI | en_US |
dc.contributor.author | Lee, YJ | en_US |
dc.contributor.author | Chao, TS | en_US |
dc.date.accessioned | 2023-03-25T02:57:13Z | |
dc.date.available | 2023-03-25T02:57:13Z | |
dc.date.issued | 2023 | |
dc.description.abstract | Germanium–tin (GeSn) epitaxy layer was prepared on an 8-in SOI wafer with a Ge buffer layer. The etching rates of different solutions for the GeSn layer were investigated. The ammonia peroxide mixture can remove the Ge buffer layer with high efficiency and selectivity to the GeSn layer. Heated ammonia solution is able to etch the Si layer without damaging the GeSn layer significantly. The two-step etching process developed in this study is conducive to achieving GeSn nanowires (NWs) by selectively etching the Ge buffer and Si bottom layers. GeSn NWFETs were fabricated and measured. The strain of the GeSn NW channels is preserved with the optimized fabrication process proposed in this study. | en_US |
dc.identifier.doi | 10.1109/TED.2023.3246952 | |
dc.identifier.isi | WOS:000943569100001 | |
dc.identifier.issn | 0018-9383 | |
dc.identifier.scopus | 2-s2.0-85149368778 | |
dc.identifier.uri | https://scholars.lib.ntu.edu.tw/handle/123456789/629647 | |
dc.identifier.url | https://api.elsevier.com/content/abstract/scopus_id/85149368778 | |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | en_US |
dc.relation.ispartof | IEEE TRANSACTIONS ON ELECTRON DEVICES | en_US |
dc.relation.journalissue | 4 | en_US |
dc.relation.journalvolume | 70 | en_US |
dc.relation.pageend | 2033 | en_US |
dc.subject | Germanium; Etching; Silicon; Epitaxial growth; Wet etching; Silicon germanium; Fabrication; Ge; germanium-tin (GeSn); nanowire (NW); selective etching; CHANNEL MOSFETS; TIN; SI | en_US |
dc.title | Fabrication of GeSn Nanowire MOSFETs by Utilizing Highly Selective Etching Techniques | en_US |
dc.type | journal article | en |
dspace.entity.type | Publication |
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