Software and Hardware Implementation of the Constrained Random Pattern Generator
Date Issued
2010
Date
2010
Author(s)
Tso, Chia-Cheng
Abstract
Constrained random simulation is the mainstream of the simulation-based functional verification methodologies for the contemporary IC (integrated circuit) design and verification flow. In this flow, designers can simply specify the constraints to confine the input behaviors of DUV (design under verification), and then the constraint solver will generate the input stimuli automatically. In order to achieve this goal, the speed of constrained random pattern generator and the quality of the patterns it generated are the most important parts that make the simulation reaching high coverage efficiently.
In this work, we analyze some previous works and implement the constrained random pattern generator. We integrate the advantages of related works, and propose the mixed Boolean and Integer decision diagram (MBIDD) for the better performance. Furthermore, we also conduct the hardware implementation of the constrained random pattern generator.
Subjects
Verification
Testbench
Constrained Random Pattern Generator
Mixed Boolean/Integer Decision Diagram
Type
thesis
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