A 2.17 mm2 125 mW reconfigurable SVD chip for IEEE 802.11n system
Journal
ESSCIRC 2010 - 36th European Solid State Circuits Conference
Pages
534-537
Date Issued
2010
Author(s)
Abstract
This paper presents a reconfigurable singular value decomposition (SVD) engine design for the IEEE 802.11n applications. This engine can support all antenna modes in an 802.11n system. The proposed design techniques can reduce decomposing latency, enhance hardware utilization, and increase system throughput. The proposed reconfigurable SVD engine design is implemented and fabricated in UMC 90 nm 1P9M CMOS technology. The maximum operating frequency is measured 101.2 MHz and the corresponding power dissipation is 125 mW. The core size is 2.17 mm 2 and the die size occupies 4.93 mm 2 .
SDGs
Type
conference paper