Bandwidth optimized motion compensation hardware design for H.264/AVC HDTV decoder
Resource
Circuits and Systems, 2005. 48th Midwest Symposium on
Journal
48th Midwest Symposium on Circuits and Systems, 2005
Pages
-
Date Issued
2005-08
Date
2005-08
Author(s)
DOI
N/A
Abstract
Design of H.264/AVC motion compensation (MC) is very challenging through the high memory bandwidth and low hardware utilization caused by the new functionalities of variable block size and 6-tap interpolation filter. In this paper, the vertically integrated double Z (VIDZ) schedule, and interpolation window reuse (IWR) and interpolation window classification (IWC) bandwidth reduction schemes are proposed to keep the MC highly utilized and save 60-80% memory bandwidth. The hardware of proposed MC is implemented at 120MHz with 47K logic gates and can support 2048 /spl times/ 1024 30fps H.264/AVC HDTV decoder with less than 200MB/s memory bandwidth.
SDGs
Type
journal article