Simultaneous routing and buffering in SOC floorplan design
Journal
IEE Proceedings: Computers and Digital Techniques
Journal Volume
151
Journal Issue
1
Pages
17-22
Date Issued
2004
Author(s)
Abstract
An EDA tool to deal with the problems of routing and buffer-insertion in system-on-chip floorplanning simultaneously is developed. This routing and buffering tool mainly consists of a Manhattan routing (MR) algorithm and a maze-based between-buffer routing algorithm. Since the processing speed of its MR is very fast, this tool can be integrated into an iterative floorplanning algorithm to promote the routability of a floorplan solution.
SDGs
Other Subjects
Congestion constraints; Cost functions; Manhattan routing (MR); Algorithms; Approximation theory; Estimation; Graph theory; Matrix algebra; Optimization; Perturbation techniques; Problem solving; Routers; Topology; VLSI circuits
Type
journal article
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