On-Chip Memory Optimization Scheme for VLSI Implementation of Line-Based Two-Dimentional Discrete Wavelet Transform

Resource

IEEE Transactions on Circuits and Systems for Video Technology 17 (7): 814-822

Journal

IEEE Transactions on Circuits and Systems for

Journal Volume

Video

Journal Issue

7

Pages

814-822

Date Issued

2007

Date

2007

Author(s)

Cheng, Chih-Chi

Huang, Chao-Tsung

Chen, Ching-Yeh

Lian, Chung-Jr

Chen, Liang-Gee

URI

Type

journal article

File(s)

Name

62.pdf

Size

716.12 KB

Format

Adobe PDF

Checksum

(MD5):297e8e357540065d0a96202fc80b0745