A Low-Power 24 GHz Phase Lock Loop with Gain-Boosted Charge Pump Embedded in 0.18 μm COMS Technology
Journal
Asia-Pacific Microwave Conference, APMC
Date Issued
2012-12
Author(s)
Abstract
A 24 GHz PLL using 0.18-μm CMOS technology is presented in this paper. To achieve the low-power consumption and low phase-noise performance, a transformerfeedback voltage control oscillator (TF-VCO) and a cascoded frequency divider including injection-locked frequency divider (ILFD) and current mode logic divider (CML) are implemented. Further- more, the gain-boosted technique was adopted in charge pump to reduce current mismatch. The phase noise of proposed PLL is measured by -83.79 dBc/Hz at 1 MHz offset and -123.61 dBc/Hz at 10 MHz offset. The power consumption is 29.8 mW (only 13.3 mW in VCO and ILFD).
SDGs
Type
conference paper