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  4. Area-efficient scalable MAP processor design for high-throughput multistandard convolutional turbo decoding
 
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Area-efficient scalable MAP processor design for high-throughput multistandard convolutional turbo decoding

Journal
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Journal Volume
19
Journal Issue
2
Pages
305-318
Date Issued
2011
Author(s)
AN-YEU(ANDY) WU  
Lin, C.-H.
Chen, C.-Y.
AN-YEU(ANDY) WU  
DOI
10.1109/TVLSI.2009.2032553
URI
http://www.scopus.com/inward/record.url?eid=2-s2.0-79151477141&partnerID=MN8TOARS
http://scholars.lib.ntu.edu.tw/handle/123456789/365389
Abstract
Most of advanced wireless standards, such as WiMAX and LTE, have adopted different convolutional turbo code (CTC) schemes with various block sizes and throughput rates. Thus, a reconfigurable and scalable hardware accelerator for multistandard CTC decoding is necessary. In this paper, we propose scalable maximum a posteriori algorithm (MAP) processor designs which can support both single-binary (SB) and double-binary (DB) CTC decoding, and handle arbitrary block sizes for high throughput CTC decoding. We first propose three combinations of parallel-window (PW) and hybrid-window (HW) MAP decoding. Moreover, the computational modules and storages of the dual-mode (SB/DB) MAP decoding are designed to achieve a high area utilization. To verify the proposed approaches, a 1.28 mm2 dual-mode 2PW-1HW MAP processor is implemented in 0.13 μm CMOS process. The prototyping chip achieves a maximum throughput rate of 500 Mb/s at 125 MHz with an energy efficiency of 0.19 nJ/bit and an area efficiency of 3.13 bits/mm2. For the multistandard systems, the expected throughput rates of the WiMAX and LTE CTC schemes is achieved by using five dual-mode 2PW-1HW MAP processors. © 2006 IEEE.
Subjects
Maximum a posteriori algorithm (MAP); multistandard platform; turbo codes
SDGs

[SDGs]SDG7

Other Subjects
Area efficiency; Area efficient; Area utilization; Block sizes; CMOS processs; Convolutional turbo codes; Dual modes; Expected throughput; High throughput; MAP decoding; Maximum a posteriori algorithm; Maximum through-put; Multi-standard; Multi-standard systems; Processor design; Prototyping; Re-configurable; Scalable hardware; Throughput rate; Turbo decoding; Wireless standards; Algorithms; CMOS integrated circuits; Convolution; Decoding; Energy efficiency; Reconfigurable hardware; Throughput; Wimax; Turbo codes
Type
journal article

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