Effects of Strain-Temperature Stress on MOS Capacitors with Ultra-thin Gate Oxides
Date Issued
2006
Date
2006
Author(s)
Lin, Chia-Nan
DOI
en-US
Abstract
As MOS devices are scaled down to the deep-submicrometer region, the thickness of silicon oxide also scales down. Based on the International Technology Roadmap for Semiconductor (ITRS), the equivalent oxide thickness (EOT) should be 0.6 nm in 2013. Although miniaturization and increasing power density are the trends in modern electronic system, the issue of thermal stress is of concern. After packing up in system, chips often suffer from the package-related stress. Many device failures are caused by the thermal-mechanical stress occurs during high temperature operations. In this thesis, we will focus on the effect of thermal-mechanical stress on oxide reliability. We will analyze the electrical characteristics and reliability of the MOS structure after receiving various mechanical stresses under an elevated temperature.
In chapter 2, we studied the electrical characteristics of MOS structures after receiving thermal treatments at 100 oC for 5 minutes with various mechanical stresses applied on the substrate. The detailed electrical characteristics on tensile-temperature samples by changing the baking time and the strength of mechanical stress are investigated. The experimental result shows the samples after long-time tensile-temperature stress and under suitable tensile stress have the best interface quality.
In chapter 3, the reliability properties of the strain-temperature samples, including time-dependent-dielectric-breakdown (TDDB) and the stress-induced-leakage current (SILC) are examined. After these tests, we find that the samples after long-time tensile-temperature stress and suitable tensile stress exhibit the improved breakdown endurance and the reduced SILC. Finally, conclusions and some other suggestions about this thesis were given.
Subjects
形變溫度
strain-temperature
Type
thesis
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