Real-Time FPGA-Based Hardware-Algorithm Co-Design for Monocular Visual Odometry on Edge Devices
Journal
IEEE Transactions on Circuits and Systems for Video Technology
Start Page
1
ISSN
1051-8215
1558-2205
Date Issued
2026-02-13
Author(s)
Abstract
Spatial computing has become a cornerstone of consumer electronics in the metaverse era, powering augmented reality (AR), virtual reality (VR) head-mounted displays (HMDs), and smart glasses. A key enabling technology for these mobile platforms is visual odometry (VO), which supports accurate motion tracking for seamless navigation and interaction. However, deploying deep learning-based VO on resource-constrained edge devices remains challenging due to high computational complexity, memory usage, and power demands. Moreover, critical operations such as feature matching, triangulation, and nonlinear optimization are notoriously intensive for embedded processors, underscoring the need for application-specific acceleration. This work presents a hardware-algorithm co-designed VO acceleration system for edge deployment, implemented on a Xilinx UltraScale+ MPSoC ZCU104. The system integrates an ARM Cortex-A53 processor, a neural network accelerator, and custom modules for feature matching and pose refinement. With hardware-aware algorithmic optimizations, the proposed design achieves a 255.6× speedup in neural inference, 13.7× acceleration for geometric modules, and an additional 2.1× gain through task-level parallelism, sustaining 30.6 FPS in real time. Compared to existing FPGA-based VO designs, our system offers the highest localization accuracy while maintaining real-time performance, demonstrating its practical viability for spatial computing in real-world scenarios.
Subjects
augmented reality
computer vision
FPGA acceleration
hardware-algorithm co-design
Visual odometry
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Type
journal article