Ultra Low Voltage And Low Leakage Delay Buffer Circuit Design

In this thesis, we propose a delay buffer which can be operated in ultra low voltage. Unlike the conventional structure which is SRAM based delay buffer. According to the function we need, we choose ring counter based delay buffer instead. We use ring counter as an address pointer. By this method, we can reduce the dynamic power. About memory cell part, we choose 10T memory cell. It is more suitable than conventional 6T memory cell in operating in subtheshold region. Therefore, the delay buffer can save a lot of power than conventional design.
In order to reduce dynamic power consumption , we use gated clock structure in the ring counter. We adequately use the characteristic of delay buffer. We can know that which part will not be used in advanced. Therefore, we will disable the clock gated tree and part of ring counter that we don''t use. It can reduce the redundant power consumption. Also, we can apply this idea to the input and output driver to reduce the dynamic power of delay buffer.
In order to make delay buffer operate in ultra low voltage, so the memory cell type we use is 10T. We can separate the path we read and write. It can avoid the data flipping when we read the stored data. Besides 10T cell type, we also apply virtual VDD and virtual ground methods to help write data into the cell and read data from the cell. Besides, we use bitline interleaving structure to avoid read failure that caused by time variation. In input and output driver tree, we modify the conventional tristate inverter. According to the requirement, we replace them with a suitable version. In input driver tree, we make it faster and lower power. In the output driver, we can operate in even more stable in low voltage than conventional tristate inverter. By the method we mentioned above, we implement a delay buffer which can be operate in 0.2 voltage. Compare with conventional 1 voltage version, the power consumption is reduced, and the leakage power reduce about 99%.