Flexible and Cost Effective Transport Stream Processor for Digital TV
Date Issued
2006
Date
2006
Author(s)
Tsai, Chia-Liang
DOI
en-US
Abstract
In recent years, a trend grows tremendously that a digital TV signal delivery system will replace the existing analog TV broadcast system. All digital TV standards are specified based on MPEG-2 system layer, such as Digital Video Broadcasting (DVB) and Advanced Television Systems Committee (ATSC), where the digital TV signals are delivered as the form of MPEG-2 transport stream. Television service providers of each country obey these standards and supply various services, such as E-learning, electrical program guide (EPG), or Interactive TV. This development also results in complicated content of transport stream. Therefore, a transport stream processor is required for every digital TV devices, and both low hardware cost and high flexibility are important requirements.
In this thesis, we propose a flexible transport stream processor hardware intellectual property (IP) of digital TV System-on-a-Chip (SoC). As a result of our analysis, it can be evidenced that the average operation count needed to process a transport stream packet is much lower than the constraint which is derived from the specification. Considering of flexibility, we propose a micro-controller based architecture of transport stream processor for digital TV. Because of efficient software/hardware partitioning, the transport stream processor can achieve high flexibility with low hardware cost. Furthermore, we design a special instruction set of micro-controller for processing data fields efficiently. Additionally, a generalized parsing engine suitable for paring grouping bit-fields is also proposed. With assistance of the generalized parsing engine, the total instruction bytes executed by micro-controller for parsing fields are greatly reduced to small size of configuration bytes executed by parsing engine. With these features, the usage of on-chip memory can be reduced with small hardware overhead in this design.
The gate count of the proposed transport stream processor is 20k while the size of on-chip memory is 36,064bits for baseline functions. The Implementation results show that the hybrid transport stream processor architecture can saves about 50% chip area as compared to other solutions. The special instruction set can save about 14.2% chip area while the parsing engine can save about 6.8% chip area compared with micro-controllers with only the general instruction set.
Subjects
傳輸資料流處理器
數位電視
transport stream processor
digital TV
Type
thesis
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