An Area Efficient High Speed SAR ADC in 0.18um
Date Issued
2014
Date
2014
Author(s)
Cheng, Li-Hsin
Abstract
SAR ADC, with simple structure and energy efficiency becomes one of the recent choices in battery-endurance concerned devices and data acquisition systems. In this thesis, we propose a “voltage-jumping” SAR architecture operating at 50MS/s in 0.18um that is area efficient and achieves high speed. The circuit solves the MSB DAC settling error physically and hence uses only 1/4 of total capacitor array area compared to the conventional structure without shrinking the size of unit capacitor. Also, the switching energy is smallest because the most critical MSB switching does not consume power and the rest of bits are switched monotonically with smaller capacitance.
As for measurement results, 0.1MHz input sinusoidal signal is fed into the ADC operating at 50MS/s, 40MS/s and 25MS/s, and the SNDR, SFDR and ENOB of the ADC are 35.31 dB, 45.81 and 5.57 bits for 50MS/s, 33.90 dB, 41.58 and 5.34 bits for 40MS/s and 33.82 dB, 39.71 and 5.33 bits for 25MS/s. The post-sim power consumption and the FoM of the ADC in 0.18um at 50MS/s are 2.3mW and 63 fJ/convstep; whereas the power consumption and the FoM of the measured circuit are 2.5mW and 1 pJ/convstep.
In future works, the problems for unsatisfied measurement in this 0.18um chip discovered are all rectified in 90nm. The post-sim 90nm “voltage-jumping” SAR ADC operating at 100MS/s with 1.3mW is present. Also, in order to accelerate the speed of ADC, a new idea of two-stage pipelined SAR ADC is launched to prevent the use of OP-amp to deliver signal to the next stage.
Subjects
逐漸趨近式類比數位轉換器
SDGs
Type
thesis
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