A leakage-current-recycling phase-locked loop in 65nm CMOS technology
Journal
IEEE Asian Solid-State Circuits Conference (A-SSCC)
Pages
137-140
Date Issued
2011-11
Author(s)
Abstract
A leakage-current-recycling technique is presented for phase-locked loops (PLLs) in nanoscale CMOS technology. The leakage current of the PMOS capacitor in a PLL is recycled to supply the power for a voltage-controlled oscillator, a divider and a dual-mode phase-frequency detector. This PLL is fabricated in a 65nm CMOS technology. The measured peak-to-peak jitter and rms jitter of this PLL at 640MHz are 52.2ps and 9.6ps, respectively. Its power consumption is 1mW for a 1.2V supply voltage.
SDGs
Type
conference paper