VLSI Placement Considering Routability and Power Consumption
Date Issued
2011
Date
2011
Author(s)
Chuang, Yi-Lin
Abstract
Placement plays a crucial role in the physical synthesis for
circuit designs. Although the placement problem has been discussed for decades, modern design challenges, such as routability and power, have demanded circuit designers to develop a more flexible placer. Unfortunately, most existing placement algorithms still focus on optimizing wirelength alone while ignoring design-related issues, e.g., power integrity and routability. Moreover, due to the advance of electronic applications, power consumption is becoming an essential metric in a design, which is not addressed in most placement algorithms either. Considering these issues when optimizing a placement can effectively reduce the burden of subsequent physical synthesis procedures (i.e., routing, power refinement, etc.) and thus improve the design closure.
In this dissertation, we propose novel algorithms for VLSI
placement problems to consider power integrity and routability. We present power-integrity (voltage-drop, in particular) aware analytical placement along with efficient voltage analysis to reduce voltage-drop violations. Then we utilize design-hierarchy information to guide the placer for routability optimization, and we also discuss how to obtain a better trade-off between voltage drops and routability. Experimental results show that our proposed
voltage-drop aware placement and routability-driven lacement can achieve respective smaller voltage drops and routing overflows than previous works.
Moreover, as power consumption becomes an essential metric, many techniques have been proposed for power reduction. Among which, pulsed-latches have emerged as a popular technique. Compared with a traditional flip-flop, a pulsed-latch is a sequential device with smaller delay and power, which is extensively adopted in modern high-performance microprocessors. In this dissertation, to address power reduction in placement, we first propose pulsed-latch aware placement to explore how to utilize pulsed-latches in an analytical placer for maintaining their timing integrity. After that, we present unified placement and clock-network co-synthesis to reduce the power consumption of a clock network while maintaining the timing integrity of pulsed-latches. Experimental results validate our pulsed-latch
aware placement and co-synthesis approach effectiveness on timing integrity and power reduction for pulsed-latch-based designs.
Subjects
Physical Design
Placement
Voltage Drop
Routability
Power
Pulsed-Latch
Type
thesis
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