A Posynomial-Based Lagrangian Relaxation Tuning Tool for Combinational Gates and Flip-Flops Sizing
Date Issued
2006
Date
2006
Author(s)
Lin, Tsung -Tse
DOI
en-US
Abstract
In this thesis, we propose a method for fast and effective combinational gates
and flip-flop sizing using Lagrangian Relaxation (LR) and posynomial model-
ing. Our algorithm optimizes a circuits delay subject to slew rate constraints,
and can readily take process variation into account. We use Synopsys liberty
format technology file to generate accurate delay models in posynomial form
for standard cells, and then we parse the input synthesized verilog file. After
reading the netlist, we do the re-formulation to represent the paths which
start from either primary input or flip-flop. After netlist re-formulation, we
have a large-scale, convex optimization problem based on the posynomial
models. Finally, we perform LR to solve for the globally-optimal set of tran-
sistor sizes for each cell and then we discretize them to the nearest drive
strength.
and flip-flop sizing using Lagrangian Relaxation (LR) and posynomial model-
ing. Our algorithm optimizes a circuits delay subject to slew rate constraints,
and can readily take process variation into account. We use Synopsys liberty
format technology file to generate accurate delay models in posynomial form
for standard cells, and then we parse the input synthesized verilog file. After
reading the netlist, we do the re-formulation to represent the paths which
start from either primary input or flip-flop. After netlist re-formulation, we
have a large-scale, convex optimization problem based on the posynomial
models. Finally, we perform LR to solve for the globally-optimal set of tran-
sistor sizes for each cell and then we discretize them to the nearest drive
strength.
Subjects
最佳化
gate sizing
Type
thesis
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