A 1.25GHz fast-locked all-digital phase-locked loop with supply noise suppression
Journal
International Symposium on VLSI Design, Automation & Test
Pages
237-240
Date Issued
2010-04
Author(s)
Abstract
A fast-locked all-digital phase-locked loop (PLL) with supply noise suppression is presented. The analysis and design of this all-digital PLL is presented. While the supply noise exits, the loop bandwidth of this all-digital PLL is dynamically adjusted to suppress the jitter. This all-digital PLL is fabricated in a 0.18 um CMOS process. It achieves the locked time of 22.5 us and 78 us with and without the fast-locked circuit, respectively. The measured peak-to-peak jitter and rms jitter are 38.9 ps and 5.9ps, respectively, at 1.25 GHz.
SDGs
Type
conference paper