Design of a Series-type Dynamic Voltage Regulator
Date Issued
2004
Date
2004
Author(s)
Wu, Sheng-Lung
DOI
zh-TW
Abstract
The power quality affects the industry to a great extent. Poor quality in the power supply, such as voltage fluctuations, may cause damage in sensitive equipments. How to maintain constant voltage profile at the load bus under disturbance conditions is of major concern in this work.
The purpose of this thesis is to analyze and design the Dynamic Voltage Regulator (DVR). This compensator employs a direct current capacitor to offer the voltage source and uses the pulse-width modulation technology to adjust the output voltage of the three-phase voltage-sourced inverter. Both steady-state performance and transient characteristic of the DVR are investigated in the thesis. In steady-state, DVR can be used to compensate the voltage drop caused by circuit reactance. In transient state, voltage sag in the load bus can be improved in a very short period by the proposed DVR.
The effectiveness of the designed DVR is first investigated by digital simulations using the PSCAD software. Then, in the experiment, the control kernel of digital system for DVR is based on a personal computer with Adventec PCL-1800 data acquisition cards. The three-phase pulse width modulation signals are generated by computer software in order to reach the objective of voltage compensation.
Finally, it is concluded from results of simulations and experiments that load bus voltage can be effectively regulated by the designed DVR.
Subjects
電壓源變流器
動態電壓調整器
DVR
VSI
Type
thesis
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